Many applications involving streaming data, such as streaming video containing embedded reference-clock information to enable clock synchronization at the receiver. An important example of such data streams are Motion Picture Expert Group (MPEG) data streams that provide an efficient format for transmitting, receiving and storing video signals in digital format—the MPEG data stream format includes a timing reference field called Program Clock Reference (PCR) or Elementary Stream Clock Reference (ESCR) that is embedded during the encoding process and serves to provide a clock synchronizing source. The PCR/ESCR field is extracted during the receive or playback process and is used to synchronize the receiving clock with the data stream rate thereby implementing clock recovery. The synchronizing or clock recovery function is implemented by a Digital Phase Locked Lop (DPLL).
FIG. 1 shows a typical DPLL used in an MPEG receiver application. The MPEG encoding is performed using a reference 27 MHz clock. To facilitate the clock recovery process at the decoder, the MPEG streams are periodically (typically every 0.1 sec) embedded with a timing reference field called Program Clock Reference (PCR). The PCR is generated as follows.
The 27 MHz system clock is given to a counter. A snapshot of the counter is taken periodically (rate at which the PCR has to be sent). The values of the counter thus obtained are stuffed into the PCR field of the MPEG stream.
On the decoding side, the clock is recovered using the values in the PCR field.
The PCR in the MPEG stream is extracted and is stored in the received PCR register (1.1). The Local PCR register (1.2) stores the values of the PCR generated by the VCXO (1.6). The contents of the counter (1.4) are loaded into local PCR register, and the MPEG stream with the PCR field updates the contents of received PCR register (1.1). The comparator (1.3) outputs an error signal depending on the difference between received PCR (1.1) and the local PCR (1.2). The error signal is used to drive a controlled clock source (1.7). Within the controlled clock source (1.7) the error signal is converted into analog voltage by the D/A converter (1.5). The analog output voltage from D/A converter (1.5) biases the VCXO (1.6) to generate the required frequency. The actual implementation may have some blocks being implemented in software. For example, the compare function can be easily implemented in the software. The D/A block may consist of a PWM generator that is programmed by the software and a low pass filter.
U.S. Pat. No. 5,473,385 describes a DPLL apparatus in which a subtractor gives the difference between received and locally generated PCR values. The output of the subtractor, which is the error value, is fed to a digital filter connected to the input of an accumulator. The accumulated error values are processed by an error signal generator, which produces a frequency adjustment signal for advancing or retarding the local oscillator frequency after gating with a selected video synchronization signal so that the clock frequency correction is performed only during the vertical synch or blanking interval and the effects of the synchronization are not visible. This technique does not permit easy modification of the characteristics of the PLL as there are no programmable features. Also, the dropping of clocks during the vertical synch incurs a significant risk in obtaining jitter-free reading of data. Finally, the implementation of this method requires major redesign of MPEG decoder circuits used in existing systems such as set-top boxes.
U.S. Pat. No. 6,072,369 uses a phase error detector, interpolator, gain calculator, digital-to-analog converter (DAC), voltage controlled oscillator (VCO) divider, and local PCR (LPCR) counter to generate the local clock signal. This scheme is implemented purely in hardware and uses analog components such as the DAC and VCO. It is therefore sensitive to noise and its characteristics are not easily modifiable.
U.S. Pat. No. 6,175,385 describes three purely digital schemes that essentially use a fixed frequency oscillator. Clock synchronization is achieved by counting clock pulses of the fixed frequency signal and adjusting the unit for incrementing or decrementing the counted value to a predetermined value in a predetermined time according to the deviation of the fixed frequency from the reference frequency. The scheme requires a redesign of almost all the blocks used to process MPEG information in the majority of existing applications. Further, this process needs to be implemented during the video-blanking interval and hence is limited to applications where such an interval is available.